Generally, in an output circuit of an integrated circuit, an electrostatic protection resistance is inserted in series between an output stage and an output pad. When the electrostatic protection resistance is not inserted in series, a size of a transistor in the output stage must be increased or an output transistor must have an electrostatic protection element. However, as a result of them, a parasitic capacitance increases, a chip size increases, or a desired characteristic cannot be accomplished.
When the electrostatic protection resistance is inserted in series between the output stage and the pad, a resistance value of the electrostatic protection resistance is set to be in a range where a condition defined for protection of an internal transistor from static electricity is satisfied. The electrostatic protection resistance is generally set to a resistance value of tens of Ω to hundreds of Ω. When the resistance value is smaller than this range, the electrostatic protection standards defined in MIL (Military) standards and EIAJ (Electronic Industries Association of Japan) cannot be satisfied.
However, when the electrostatic protection resistance is connected to the output circuit, the output characteristic reduces. The reduction of output characteristic when the electrostatic protection resistance is connected to the output circuit will be described below.
FIG. 1 is a diagram showing an output circuit using an operational amplifier. In the output circuit shown in FIG. 1, an electrostatic protection resistance RESD is connected between an output of an analog amplifier circuit 101 and an output pad 102. The analog amplifier circuit 101 includes a differential amplifier stage 103 and the output stage 104. The output stage 104 includes a PMOS transistor MP1 having a source connected to a power supply of a positive power supply voltage VDD and an NMOS transistor MN1 having a source connected to a power supply of a negative power supply voltage VSS. Two outputs of the differential amplifier stage 103 are connected to the respective gates of the PMOS transistor MP1 and the NMOS transistor MN1. One end of the electrostatic protection resistance RESD is commonly connected to the respective drains of the PMOS transistor MP1 and the NMOS transistor MN1, and the other end is connected to the output pad 102. The one end of the electrostatic protection resistance RESD is connected to an inversion input terminal of the differential amplifier stage 103, and a feedback operation is perform. The output stage 104 further includes phase compensation capacitances CP and CN. Respective one ends of the phase compensation capacitances CP and CN are connected to the respective drains of the PMOS transistor MP1 and the NMOS transistor MN1, and respective other ends of the phase compensation capacitances CP and CN are connected to the differential amplifier stage 103.
It should be noted that for the electrostatic protection, an electrostatic protective diode is generally used in parallel actually in addition to the electrostatic protection resistance RESD. However, since the diode is not directly related to the present invention, illustration of it is removed and the description of it is omitted.
In the circuit configuration shown in FIG. 1, the commonly-connected drains of the PMOS transistor MP1 and the NMOS transistor MN1 are an output of the analog amplifier circuit 101. Since the feedback operation is performed from this output to the inversion input terminal, a so-called voltage follower connection is configured and a same voltage as a voltage supplied to a non-inversion input terminal is outputted from the output of the analog amplifier circuit 101. Then, the voltage outputted from the analog amplifier circuit 101 is finally outputted from the output pad 102 via the electrostatic protection resistance RESD. In the circuit configuration shown in FIG. 1, an output waveform is degraded due to an influence of the electrostatic protection resistance RESD. FIG. 2 is illustrated by plotting output waveforms when a rectangular wave is supplied to the non-inversion input terminal of the analog amplifier circuit 101 in the state that a value of the electrostatic protection resistance RESD changed. As understood from FIG. 2, as the electrostatic protection resistance RESD becomes larger, the output waveform becomes duller. When the electrostatic protection resistance RESD is zero, the characteristic ideally becomes the best. However, since the electrostatic protection resistance RESD of the resistance value determined to satisfy the standard has to be inserted actually, the output characteristic is consequently limited by the electrostatic protection resistance RESD.
On the other hand, a technique for reducing influence of an electrostatic protection resistance in an output circuit of a digital circuit is disclosed in Japanese Patent Publication (JP 2001-358300A: patent literature 1). Referring to FIG. 3, the output circuit described in the patent literature 1 will be described. The output circuit shown in FIG. 3 includes n PMOS transistors MP1 to MPn, n NMOS transistors MN1 to MNn, PMOS electrostatic protection resistances RP1 to RPn, NMOS electrostatic protection resistances RN1 to RNn, an internal circuit 105, an output terminal pad 106, and an inverter 107. The PMOS transistors MP1 to MPn are commonly connected to a power supply of a positive power supply voltage VDD at their sources, and the NMOS transistors MN1 to MNn are commonly connected to a power supply of a negative power supply voltage VSS at their sources. The PMOS electrostatic protection resistances are respectively connected to drains of the PMOS transistors MP1 to MPn, and the NMOS electrostatic protection resistances for RN1 to RNn are respectively connected to drains of the NMOS transistors MN1 to MNn. The inverter 107 is connected to the output terminal pad 106 at the input, and is connected to the internal circuit 105 at the output. The respective gates of the PMOS transistors MP1 to MPn and the respective gates of the NMOS transistors MN1 to MNn are commonly connected to the output of the internal circuit 105. In addition, the PMOS electrostatic protection resistances RP1 to RPn are connected between the drains of the PMOS transistors MP1 to MPn and the output terminal pad 106, and the NMOS electrostatic protection resistances RN1 to RNn are connected between the drains of the NMOS transistors MN1 to MNn and the output terminal pad 106.
Referring to FIG. 3, the PMOS electrostatic protection resistances RP1 to RPn and the NMOS electrostatic protection resistances RN1 to RNn are inserted in order to avoid destruction of the MOS transistors due to electrostatic surge, and the resistance values thereof are approximately tens of Ω to hundreds of Ω in general depending on a device process. The resistance values of the electrostatic protection resistances RP1 to RPn and RN1 to RNn vary depending on actual values of the respective device processes, but are required to be set to resistance values satisfying the standard. A voltage drop due to the electrostatic protection resistance causes the characteristic degradation of the output circuit as described above. However, by connecting a plurality of the MOS transistors in parallel as shown in FIG. 3, a current can be distributed into n electrostatic protection resistances. That is, the current flowing through one electrostatic protection resistance is 1/n of the original current. In this manner, the voltage drop due to the current flowing through the respective electrostatic protection resistance also is 1/n, and thus the characteristic degradation of the output circuit can be prevented.
Citation List:
Patent Literature 1: JP 2001-358300A